1. Field of the Invention
The present invention relates to a connecting mechanism between a terminal or the like of a personal computer or an on-line system and a memory card which is connected detachably thereto.
2. Description of the Related Art
FIG. 1 schematically illustrates a configuration of a conventional connecting mechanism for a memory card, and a state in which a memory card 21 is connected to terminal equipment (not shown). The memory card 21 comprises a semiconductor memory 10, a buffer circuit 1, a supply voltage detecting circuit 11, a reverse charging prevention diode 12, a current limiting resistor 13, a battery 14, and a card-side connector 16. A static RAM is used as the semiconductor memory 10, and a buffer circuit 1 is constituted by an IC. The card-side connector 16 mounted on the memory card 21 has card-side connector terminals 16a-16n. All the terminals 16a and 16n have the same length. Meanwhile, a terminal equipment-side connector 17 is mounted on the side of the terminal equipment and comprises terminal equipment-side connector terminals 17a to 17n. All of these terminals 17a to 17n have the same length. A terminal equipment-side power input line 18 supplies power to the memory card 21, and the voltage of a grounding line 20 constitutes a reference voltage for the terminal equipment and the memory card 21 and is normally 0 V. Input/output lines 19b to 19 are used for input and output signals for writing in and reading from the semiconductor memory 10. In addition, pull-down resistors 7b to 7 respectively connected to output lines 19b to 19 between the card-side connector 16 and the buffer circuit 1 as well as a pull-up resistor 7 connected to a card enable signal line 19 among the input/output lines are designed to stabilize the levels of the input/output lines 19b to 19 on the side of the card 21 to a low (L) level or a high (H) level.
Next, a description will be given of the operation of the prior-art connecting mechanism. In FIG. 1, when the memory card 21 is connected to the terminal equipment and the voltage of the power input line 18 reaches a predetermined level, the supply voltage detecting circuit 11 supplies to an internal power line 15 the power from the power input line 18, supplies an ON/OFF signal 11a to the buffer circuit 1, and sets the buffer 1 in a connected state. In addition, when the voltage of the power input line 18 drops below a predetermined level, the supply voltage detecting circuit 11 cuts off the power input line 18 electrically and also sets the buffer circuit 1 in a cut off state by means of the ON/OFF signal 11a. When the voltage of the power input line 18 reaches a predetermined level or more, the power from the power input line 18 is supplied to the internal power line 15, and the buffer circuit 1 is set in a connected state. The voltage Vbb of the battery 14 is normally 3 V, but no current flows from the internal power line 15 through the action of the reverse charging prevention diode 12. In this state, the writing and reading of data with respect to the semiconductor memory 10 from the terminal equipment is possible through the input/output lines 19b to 19. The input/output lines 19b to 19 include an address bus, a data bus, a control signal line (including the card enable signal line 19), and the like. Since the operation of the semiconductor memory 10 is generally known, a description thereof will be omitted. Next, when the voltage from the power input line 18 has reached a predetermined level or below, the power from the power input line 18 on the side of the terminal equipment is cut off by the operation of the supply voltage detecting circuit 11, and, at the same time, the buffer circuit 1 is set in a cut-off state by the action of the ON/OFF signal 11a. Accordingly, the power from the battery 14 is supplied to the internal power line 15 through the current limiting resistor 13 and the reverse charging prevention diode 12, so that the data stored in the semiconductor memory 10 is retained. The voltage of the power input line 18 is generally 4.5 to 5.5 V, while a predetermined level at which the supply voltage detecting circuit 11 effects a changeover of the power is in the neighborhood of 3.9 to 4.2 V.
In the above, the basic operation of the memory card 21 has been described. Next, a description will be given of a case where the memory card 21 is inserted into or removed from the terminal equipment. Specifically, a description will be given of a case where the memory card 21 is pulled out in a state in which the power is supplied from the terminal equipment to the memory card 21 via the power in out line 18 and power input terminal 17a and the power is supplied to the internal power line 15 by means of the supply voltage detecting circuit 11 as well as in a line-activated state in which an "H" level signal is applied to the card enable signal line 19 (at which the memory card 21 is in an non-operative state), which is one of the input/output lines from the terminal equipment, while an arbitrary signal is applied to the other input/output lines 19b to 19. When the grounding line 20 is separated in advance of the other terminals and when one of the signals of the input/output lines 19b to 19 is at "H" level and another is at "L" level, a loop current I.sub.1 (see FIG. 2) flows which passes through the memory card 21 from the terminal equipment and then returns to the terminal equipment. As a result, as shown in FIG. 1, an abnormal current I flows from the battery 14 via the current limiting resistor 13, the reverse charging prevention diode 12, the internal power line 15, the buffer circuit 1 and the semiconductor memory 10. If it is assumed that the value of this abnormal current I is I, the voltage at the power supply is Vcc, the voltage of the batter 14 is Vbb, and the resistance of the current limiting resistor 13 is R, the voltage Vdd of the internal power line 15 drops instantly to the value shown by the following Formula (1): EQU Vdd=Vcc-{R.multidot.I+(forward voltage of the diode 12)} (1)
The value of R i generally about 1.5 k.OMEGA.. In the other hand, since the minimum holding voltage for the data stored in the semiconductor memory 10 is 2 V, if it is assumed that the abnormal current I is 1 mA, and the forward voltage of the reverse charging prevention diode 12 is 0.6 V, the voltage Vdd of the internal power line 15 becomes 0.9 V and becomes smaller than the minimum holding voltage for holding the data stored in the semiconductor memory 10. Therefore, the data stored in the semiconductor memory 10 will disappear. The value of this abnormal current I becomes greater than 1 mA.
Referring now to FIG. 2, a description will be given of the mechanism of occurrence of the above-described loop current. FIG. 2 illustrates two elements in the buffer circuit 1 so as to facilitate an understanding of the mechanism of occurrence of the loop current. To facilitate the description, the internal structures of buffer elements 1b, 1c are respectively shown as equivalent circuits comprising only input circuits such as diodes 2b, 2c and buffer portions 3b, 3c. In addition, FIG. 2 shows input signal lines 5b, 5c from the card-side connector 16 and output signal lines 6b, 6c to the semiconductor memory 10. As described above, the buffer circuit 1 is constituted by an IC such as a CMOS IC, a TTL IC, or a LSTTL IC, but parasitic transistors 4B, 4C shown by broken lines in FIG. 2 are employed naturally. As described above, if, during the withdrawal of the memory card 21, the grounding line 20 is separated in advance of the other terminals, and if one of the signals of the input/output lines 19b to 19 is at "H" level and another is at "L" level, the "H" level signal input from the terminal equipment via the input signal line 5B flows from the pull-down resistor 7b to ground. This current flows from the internal grounding line 9, to between the base and the emitter of the parasitic transistor 4c and constitutes a base current, and further passes through the input signal line 5c and returns to the terminal equipment, thereby constituting the loop current I.sub.1. Consequently, an overcurrent I.sub.2 flows from the internal power input line 8 to between the collector and the emitter of the parasitic transistor to the input signal line 5c. Each internal power input line 8 is connected to the internal power line 15 shown in FIG. 1. Accordingly, as described above, the abnormal current I flows to the internal power line 15 via the battery 14, the current limiting resistor 13, and the reverse charging prevention diode 12. In cases where the grounding line 20 makes contact by lagging behind the other terminals during insertion of the memory card 21, this abnormal current I occurs with a similar mechanism.
At present, as for power input terminal 17a as well as the terminals 17b to 17n of the terminal equipment-side connector 17, those having the same length or having some differences in the length are used. However, there are manufacturing tolerances in the dimensions of the terminals 17a to 17n. In addition, an electrical sequence for coping with diagonal insertion and withdrawal is not provided so as to allow the grounding terminal to make contact in advance of the other terminals during insertion and to be separated by lagging behind the other terminals during withdrawal. Therefore, there is a possibility that the data stored in the semiconductor memory 10 may disappear.
On the other hand, as shown in FIG. 3, during the insertion and withdrawal of the memory card 21, chattering occurs in a signal (a) of the terminals other than the grounding terminal and a grounding signal (b) of the grounding terminal, respectively. With respect to the period of occurrence of this chattering, no electrical sequence has been adopted by taking into account the aforementioned manufacturing tolerances in the length of terminals and the diagonal insertion. In addition, this chattering often exerts an adverse effect on the terminal equipment, possibility resulting in a malfunctioning of a CPU on the terminal equipment side. The electrical sequence referred to here means that the grounding terminal always makes contact in advance of the other terminals during insertion, and is always released after the other terminals during withdrawal.
As described above, in the conventional connecting mechanism, an electrical sequence is not necessarily adopted in the terminals 16a to 16n and 17a to 17n of the card- and terminal equipment-side connectors 16, 17. Accordingly, during insertion and withdrawal with the lines of the memory card 21 kept in an active state, the loop current can flow from the terminal equipment and return to the terminal equipment via the buffer circuit 1 of the memory card 21. As a result, an abnormal current can flow from the grounding terminal via the battery 14, the current limiting resistor 13, and the reverse charging prevention diode 12. Therefore, since this abnormal current causes the voltage of the internal power line 15 to drop, there has been the possibility that the data stored in the semiconductor memory 10 may disappear and the buffer circuit 1 or the semiconductor memory 10 may be destroyed. Meanwhile, with respect to the terminal equipment as well, if the CPU on the terminal equipment side and the memory card 21 are directly connected to each other, there has been a problem in that a malfunctioning can occur in the CPU of the terminal equipment due to the chattering occurring during insertion or withdrawal of the memory card 21.